library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.typeDefinitions.all;

entity fetchInterstageReg is
  port (
    clk            : in  std_logic;
    nReset         : in  std_logic;
    holdStage      : in  std_logic;
    invalidate     : in  std_logic;
    nPC_in         : in  std_logic_vector(31 downto 0);
    instruction_in : in  std_logic_vector(31 downto 0);
    instruction    : out std_logic_vector(31 downto 0);
    nPC            : out std_logic_vector(31 downto 0));
end interstageReg;

architecture interstageReg of interstageReg is

  signal r_instruction, n_instruction : std_logic_vector(31 downto 0);
  signal r_nPC, n_nPC                 : std_logic_vector(31 downto 0);
  
begin  -- interstageReg  

  registers : process (clk, nReset, n_nPC, n_instruction)
  begin

    -- one register if statement
    if (nReset = '0') then
      -- Reset here
      
      r_instruction <= (others => x"00000000");
      r_nPC         <= (others => x"00000000");
      
      
    elsif (rising_edge(clk)) then
      -- Set register here
      
      r_instruction <= n_instruction;
      r_nPC         <= n_nPC;
      
    end if;
    
  end process;


  -- outputs: 
  nextState : process (holdStage, invalidate, r_instruction, r_nPC)
  begin  -- process nextState
    if(invalidate = '1') then
      n_instruction <= (others => x"00000000");
      n_nPC         <= (others => x"00000000");      
    else
      if(holdStage = '1') then
        n_instruction <= r_instruction;
        n_nPC <= r_nPC;
      else
       n_nPC <= nPC_in;
       n_instruction <= instruction_in;
      end if;
    end if;
    
    
  end process nextState;

  

end interstageReg_arch;
